1. Field of the Invention
This invention relates to a controller for data storage systems, and more particularly to a control system for regulating the flow of data through a buffer memory in a mass data storage system controller.
2. Related Art
Mass data storage systems are used in conjunction with computers to store large quantities of data. Such mass data storage systems include, for example, direct access storage devices using magnetic media or optical media.
Mass data storage systems typically use a controller subsystem to control the operation of the storage system and execute commands from a computer system. Such commands include READ and WRITE commands. For example, a magnetic or optical disk drive that is coupled to a computer via a Small Computer System Interface ("SCSI") uses a controller to interpret commands that conform to the SCSI protocol and to control the operation of the disk drive such that those commands are properly executed. Such controllers typically have a buffer memory for temporarily storing data that is to be read from or written to the storage system.
A buffer memory serves several functions, including adapting the input and output rates of the storage system to the input and output rates of the computer interface, and temporarily holding data before release until such time as the validity of the data is determined by means of an error correction process. Typical sizes of such a buffer memory are approximately 48,000 to 64,000 bytes of data.
Controllers in the past have been designed around a microprocessor that, under computer program control, monitors and controls all operations in the controller. For example, if a sector (typically 180 to 512 bytes) of data is read from a storage system into a buffer memory, the microprocessor controls every state of the transfer from the disk into the buffer memory, validation of the data in the buffer memory (by means of an error correction code ("ECC") also read from the storage system), and the release of valid data from the buffer memory to the computer interface. Such control by the microprocessor is typically initiated and controlled by the receipt of one or more interrupt signals from the storage system, the buffer memory, or the computer interface.
In the past, commonly available microprocessor technology has been adequate to handle such programmed control tasks, because the serial data rate of storage systems has been in the range of 10 to 16 MHz. However, market demands for increasing data rates have pushed serial data transfer speeds into the range of 32 to 48 MHz, and it is predictable that the data transfer rate will increase in the future. Reasonably priced microprocessors are not capable of handling and processing interrupt signals for each data sector at such high serial data transfer rates.
It is therefore desirable to provide a means that eliminates the need for microprocessor control of a substantial part of the data transfer process between a computer interface and a mass data storage system. Such a means can permit the continued use of commonly available, low priced microprocessor technology without requiring more expensive microprocessors capable of operating at higher data rates.
The present invention provides such a means using low-cost components to substantially bypass direct control of data flow by the controller's microprocessor.